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Abstract

With the advent of System-on-Chip (SoC), intense research efforts are being carried out in
order to find efficient practical solutions for testing deeply embedded, mixed-signal cores.
Due to restricted access, a built-in self-test (BIST) of mixed-signal cores is in many cases a
preferred alternative to a conventional test using external automatic test equipment (ATE).
BIST solutions to the problem of an analog-to-digital converter (ADC) test have been
developed and practiced over the past years; their application in a SoC test infrastructure,
however, remains an open issue.
In the ADC test, a histogram-based test and an oscillation-based test are the two
approaches most suitable for BIST implementations.
The histogram-based test involves the application of an analog signal to the ADC input and
a record of the number of times each code appears on the ADC outputs. These recorded
samples are then used with theoretical samples in a complex computation to determine the
ADC parameters, i.e., offset, gain, differential and integral non-linearity.
In an oscillation-based test (OBT), the circuit-under-test is converted into an oscillator and
possible faults are assumed to manifest in the oscillation frequency. The OBT method has
been practiced mostly in the area of different classes of filters. It has been only rarely applied
in practice for testing ADCs.
Implementations of the histogram-based test and the oscillation-based test of ADCs in a
test wrapper in a SoC are related to the problems of the minimization of the BIST overhead,
test time and the achieved measurement accuracy. So far, most of these problems have been
addressed only theoretically. The lack of reported experimental evidence encouraged our
work on the design of a histogram-based test technique in a IEEE Std 1500 wrapper together
with a thorough evaluation of the implemented test infrastructure on experimental case
studies. We implemented three extreme versions of the histogram-based BIST with regards to
the test-time/hardware-overhead trade-off and scalability. The IEEE Std 1500 test wrapper
with the above BIST structures was implemented in a Spartan3 XC3S200 FPGA. The
MAX165 (an 8-bit microprocessor compatible ADC) was initially chosen as the unit-under-
test. The measured parameters of the employed ADC were in conformance with the
specifications provided by the manufacturer, which demonstrates the feasibility of the
histogram-based test technique with the implemented test structures.
So far, most of the OBT-related work has been directed either towards the problem of
modification of a given circuit-under-test into an oscillator, or towards the analysis of
detected faults (exploring ways to increase fault coverage or even trying to perform a fault
diagnosis). Little attention has been paid to the measurement accuracy of the developed OBT
solutions. Our feasibility studies of OBT-based BIST performed on a simulation environment
using Matlab Simulink revealed an inherent measurement uncertainty of the approach. The
measurement of the oscillation period is precise, but due to the arbitrary input signal phase
shift and with respect to the ADC conversion two oscillation periods are possible. This in turn
manifests itself as a measurement uncertainty. We further elaborated this issue and derived a
theoretical background for computing the measurement uncertainty of the approach.